/*
 * Copyright : (C) 2024 Termony Technology, Inc. All Rights Reserved.
 */

#ifndef RK_PMU1_IOC_HW_H
#define RK_PMU1_IOC_HW_H

#ifdef __cplusplus
extern "C"
{
#endif

/** @name Register Map
 *
 * Register offsets for the PMU1_IOC.
 */
#define RK_PMU1_IOC_GPIO0A_IOMUX_SEL_L_OFFSET   0x0000U /* GPIO0A IOMUX Select Low bits */
#define RK_PMU1_IOC_GPIO0A_IOMUX_SEL_H_OFFSET   0x0004U /* GPIO0A IOMUX Select High bits */
#define RK_PMU1_IOC_GPIO0B_IOMUX_SEL_L_OFFSET   0x0008U /* GPIO0B IOMUX Select Low bits */
#define RK_PMU1_IOC_GPIO0A_DS_L_OFFSET          0x0010U /* GPIO0A Driver Strength Control Low bits */
#define RK_PMU1_IOC_GPIO0A_DS_H_OFFSET          0x0014U /* GPIO0A Driver Strength Control High bits */
#define RK_PMU1_IOC_GPIO0B_DS_L_OFFSET          0x0018U /* GPIO0B Driver Strength Control Low bits */
#define RK_PMU1_IOC_GPIO0A_P_OFFSET             0x0020U /* GPIO0A Pull-up/down Control */
#define RK_PMU1_IOC_GPIO0B_P_OFFSET             0x0024U /* GPIO0B Pull-up/down Control */
#define RK_PMU1_IOC_GPIO0A_IE_OFFSET            0x0028U /* GPIO0A Input Enable Control */
#define RK_PMU1_IOC_GPIO0B_IE_OFFSET            0x002CU /* GPIO0B Input Enable Control */
#define RK_PMU1_IOC_GPIO0A_SMT_OFFSET           0x0030U /* GPIO0A Schmitt Trigger Control */
#define RK_PMU1_IOC_GPIO0B_SMT_OFFSET           0x0034U /* GPIO0B Schmitt Trigger Control */
#define RK_PMU1_IOC_GPIO0A_PDIS_OFFSET          0x0038U /* GPIO0A Auto Pull-up/down disable Control */
#define RK_PMU1_IOC_GPIO0B_PDIS_OFFSET          0x003CU /* GPIO0B Auto Pull-up/down disable Control */
#define RK_PMU1_IOC_XIN_CON_OFFSET              0x0040U /* OSC control Register */

#ifdef __cplusplus
}
#endif

#endif /* RK_PMU1_IOC_HW_H */